This invention relates generally to semiconductor memories and more particularly, to a semiconductor memory suitable for suppressing a spike current of a dynamic MOS memory.
As the memory capacity of dynamic MOS memories has been increased, a spike current flowing through a chip has become one of the significant design factors in order to suppress noise. In order to suppress a charging current that flows when charging data lines simultaneously at the time of precharge, there has been employed in the past a method which divides a memory array into a plurality of sub-arrays and staggers the timing of the spike current (charging current) applied to each sub-array so as to reduce effectively the spike current of the chip as a whole, as described, for example, in IEEE J. "Solid-State Circuits", pp. 585-590, October 1984.
However, this method deals with the precharge spike current after completion of an amplification operation where a small signal voltage is read out from a memory cell and is amplified and the data line voltage reaches 0 V or 5 V. The precharge method precharges the data line to a V.sub.cc (power source voltage, ordinarily 5 V). In other words, the method does not deal with the timing of the small signal voltage from the memory cell, that is, the spike current at the time of amplification. However, as the memory capacity of memories has been increased in recent years, the increase in consumed power resulting from the increase of the charging/discharging current of the data line has become a critical problem. To solve this problem, a system which precharges the data line to V.sub.cc /2 (2.5 V) and a system which combines CMOS sense amplifiers as a sense amplifier, that is, sense amplifiers consisting of N-channel MOS transistors, with sense amplifiers consisting of P-channel transistors have become important. The system, however, causes a spike current to flow at the time of amplification which is a problem as will be described elsewhere. If the spike current becomes great at the time of amplification, noise is induced inside the semiconductor chip and stable operation at the time of amplification becomes impossible. In such systems, the width of the aluminum wiring has been increased, for example, to solve this problem in, but this method invites another problem in that the chip area increases remarkably. Unlike the V.sub.cc precharge system, the current flowing through the current line at the time of precharge in this system is almost negligibly small because precharge may be made inside the data line. Even if division of the driving system used for the conventional V.sub.cc precharge system is applied to such a V.sub.cc /2 precharge system, stable operation is not possible because noise becomes too great. In other words, let's consider the case where pulses are applied to word lines of a certain two sets of sub-arrays and small signal voltages appear from the memory cells on the respective word lines. Under this state, let's consider the time zone in which the sense amplifier of a certain subarray starts operating but the sense amplifier in another sub-array is still inoperative. At this time, the voltage change of the data line inside the sub-array whose sense amplifier is operating is great, and this is coupled as noise with another sub-array whose sense amplifier is still inoperative, through various parasitic capacitances. In consequence, the sub-array under the inoperative state cannot operate stably due to the noise when it tries to amplify the signal voltage when it subsequently enters the operative state.
For the reason described above, it is very important in the V.sub.cc /2 precharge system to reduce the spike current inside the sub-arrays at the time of amplification in order to reduce the chip area and to insure stable operation. These problems will be further described by use of a circuit produced tentatively by the inventors of the present invention.
FIGS. 2A, 2B and 3 show an structural example of a 1M-bit dynamic memory produced by the present inventors.
Incidentally, this circuit is produced tentatively with reference to K. Sato et al "A 20ns Static Column 1 Mb DRAM in CMOS Technology", ISSCC Digest of Technical Papers, pp. 254, February 1985, shown in FIG. 1A and Japanese Patent Laid-Open No. 198592/1982.
The sense system in this circuit is simplified for ease of description. Address signals various clock signals or various clock signals inherent to an address multiplex system are also omitted.
FIG. 2A shows a block BLK.sub.0 consisting of 256-bit subarrays MA, sense amplifiers NS consisting of N-channel MOS transistors, sense amplifiers PS consisting of P-channel transistors and precharge circuits PC. Folded data line cells are used for the memory cells MC. Such memory cells are described in detail in K. Itoh and H. Sunami, "High Density One-Device Dynamic MOS Memory Cells", IEE PROCE., Vol. 130, ptl, No. 3, June, 1983, pp. 127, for example.
1024 memory cells are connected to one word line, and the precharge circuits PC and the sense amplifiers PS, NS are connected to the corresponding 1024 pairs of data lines (D.sub.0, D.sub.0, . . . D.sub.1023, D.sub.1023). Four such blocks constitute the 1M-bit chip.
Next, the operation of the block shown in FIG. 2A will be explained with reference to the timing chart of FIG. 3. In FIG. 3, symbol .phi.P represents a precharge signal, W.sub.0 -W.sub.225 are voltages applied to the word lines, .phi..sub.ND and .phi..sub.PD are voltages of the sense driving circuits consisting of N- and P-channel MOS transistors, respectively, and i.sub.N and i.sub.P are currents flowing through common driving lines CL.sub.00 and CL.sub.01.
After all the data lines D.sub.0 -D.sub.1023 and the driving lines CL.sub.00, CL.sub.10 of the sense amplifiers NS, PS, and the like are charged to a half voltage (V.sub.cc /2; ordinarily V.sub.cc =5 V so V.sub.cc /2=2.5 V), an X decoder (XDEC) and an X driver (XD) are selected by a plurality of address signals (not shown). Thereafter, the clock .phi..sub.x is applied and a pulse is applied to the selected word line (e.g. W.sub.0). Accordingly, the read signal voltage is outputted from the 1024 memory cells connected to the selected word line W.sub.0 in accordance with the data stored in the capacitor C.sub.s to the corresponding data lines. This voltage is substantially proportional to V.sub.ST C.sub.S /C.sub.D with C.sub.D representing the parasitic capacitance of the data line and V.sub.ST being the stored voltage in the capacitor C.sub.S.
Ordinarily, C.sub.S /C.sub.D is a small value and V.sub.ST is 5 V when the logic is "1" and 0 V when the logic is "0". Accordingly, the read signal voltage is about 200 mV. FIG. 3 shows only the voltage waveform to the data line D.sub.0 when the 5 V voltage is stored in the memory cells connected to the data line D.sub.0. Since no memory cell is connected to the other data line D.sub.0 of the data line pair, the voltage remains 2.5 V. Incidentally, a dummy cell may be connected to the data line D in order to offset the noise at the time of read-out as is well known in the art, but such an arrangement is hereby omitted because it is irrelevant to the subject matter of the present invention. Next, when .phi..sub.ND and .phi..sub.PD are ON, the drivers ND and PD operate and the sense amplifiers NS and PS operate in response thereto so that the small signal voltages on the data line pair are differentially amplified. Thereafter, a Y decoder (YDEC) and a Y driver (YD) selected by a plurality of address signals select Y.sub.0, for example, and the amplified signals on the data line pair D.sub.0, D.sub.0 are outputted to an I/O line pair and become data output D.sub.0. The write operation is made in the reverse route to the read operation as is well known, so that the data input D.sub.i is controlled by a write control signal WE and desired data is written into the selected memory cell. As described clearly in the afore-mentioned references, Y.sub.0 -Y.sub.1023 are wired in common to each sub-array by three-dimensional wiring and control data exchange between the data line pair inside each sub-array and the I/O line. Though four I/O line pairs belonging to each block BLK.sub.0 -BLK.sub.4 exist in FIG. 2B, it is possible to employ the construction in which they independently make the data exchange with circuits outside the chip in parallel with the chip or the construction in which the four I/O line pairs are decoded by address signals to form one set of D.sub.i and D.sub.0 when viewed from outside the chip. However, since they are irrelevant to the subject matter of the present invention, the detailed description is hereby omitted.
The problem with the operation of the device that has been described so far is that the currents flowing through the common driving lines CL.sub.00, CL.sub.10 are as great as from 200 to 300 mA because the 1024 sense amplifiers NS, and PS operate simultaneously inside one block. Ordinarily, CL.sub.00, and CL.sub.10 wiring is made by aluminum in order to prevent the voltage drop of the wiring resistance due to the excessive current and to reduce the noise, but the wiring must be from 50 to 100 .mu.m width, for example, in order to accommodate the periodic increases in current. In a 1M-bit memory, a data line is divided by four in order to reduce the parasitic capacitance and to increase the signal voltage from the memory cell, as shown in FIG. 2B. If the memory capacity is to be further increased, the number of divisions of the data line must also increase causing wiring width of CL.sub.00, CL.sub.10 to increase, which results in the further increase of the chip area.